In the thermal and chemical processing of semiconductor wafers, it is highly desirable to very accurately control the thermal and gaseous treatment to which the wafers are exposed during processing. Typically, batches of wafers are processed in a semiconductor processing furnace having an processing chamber which can be controllably enclosed. The processing environment within the enclosed processing chamber is carefully controlled to effect the desired processes.
Early designs for semiconductor diffusion processing furnaces were configured with the wafer array and processing chamber in a horizontal orientation. This was apparently done in an attempt to obtain products having more uniform characteristics. However, the desired uniformity was not easily achieved and horizontal furnaces suffered some disadvantages because of their configuration. In some furnaces it became difficult to achieve uniformity when performing high-pressure oxidation or silicon deposition processes. These furnaces also proved difficult in achieving desired quality levels for the wafer or other semiconductor articles being processed.
In response to problems experienced by horizontal diffusion furnaces, alternative designs were developed. Furnaces having vertically arranged wafer arrays and processing chambers were made in an effort to provide better control of temperature and other processing parameters. U.S. Pat. No. 4,738,618 issued to Robert G. Massey et al. On Apr. 19, 1988 shows a vertically oriented thermal processor having a vertically adjustable furnace assembly and process tube. The process tube, constructed from a quartz bell jar, is vertically moveable in up and down directions within a supporting framework in conjunction with a likewise moveable furnace assembly. Additionally, the furnace assembly and process tube are moveable together between up and down positions, as well as independently of one another. Heat is supplied to the thermal processor when the furnace assembly and process tube are both lowered into the down position by controlling operation of heating elements within the furnace assembly. To cool the process tube within the thermal processor, the operation of the heating elements is regulated such that interior heat is dissipated to the exterior of the processor by convection. Although this vertical furnace design provided significant improvements, further improvements were found desirable to achieve greater temperature uniformity and better control over other processing parameters.
One design challenge associated with the above vertical furnace design included a tendency for the thermal processor to collect deposits of contaminants on the inner surface of the quartz process tube under certain treatment procedures. In an effort to address these problems, U.S. Pat. No. 5,000,682, issued to Donald W. Haight et al. on Mar. 19, 1991 presented a vertical furnace design that separates the furnace into a pre-heat and post-cool area in which the wafers are processed and in which gaseous or vapor treatments are conducted.
Another area of continuing design challenge is to more quickly cool the wafer array and processing chamber after high temperature thermal processing has been completed. Rapid cooling needs to be done in a uniform manner to help minimize the risks of processing variations between wafers and between different batches of wafers.
Relatively rapid but uniform cooling is also desired in order to minimize overall thermal exposure. Thermal exposure can have deleterious effects upon layers of the semiconductor article which have been previously processed. This is widely recognized by the term thermal budget which indicates that a wafer has a budget for the degree of exposure to elevated temperature processes. The effects are not linear with temperature, but instead have increasingly significant effects with higher temperatures. Examples of deleterious effects associated with added high temperature exposure include temperature induced crystal defects or deviations, and undesired additional diffusion of dopants or other materials within the matrix of the semiconductor article being processed. Thus it is desirable to bring a batch of wafers being processed within a furnace up to a desired processing temperature relatively rapidly, and to cool the wafers also in a relatively rapid manner. These goals are further emphasized because overall processing time and costs can be reduced if the processing time can be reduced.
Another challenge in the design of semiconductor thermal processors is with regard to more quickly achieving a desired temperature environment within the process chamber so that wafers or other semiconductor articles are heated at uniform rates and to uniform temperatures. The desired uniformity is variable in both axial and radial directions relative to the array of wafers being processed. Particularly, there is a need to realize a desired, or pre-defined thermal processing model in the processing chamber during a processing step in order to produce processed wafers having better uniformity. Particularly, problems can be encountered due to axial and radial variations in temperature between different regions of the processing chamber. The ability to control these variations becomes more difficult as faster thermal ramp-up and ramp-down targets are attempted in the process chamber. Therefore, improvements in furnace design are necessary in order to achieve an aggressive reduction in cycle time without a degradation in uniformity of processed wafers. The arrangement of heating elements and cooling fluids used in and around the processing chamber creates a delay in thermal response of the process chamber temperature which makes accurate dynamic control of the temperature during ramp-up, ramp-down and changing temperature rate conditions particularly difficult. A further problem posed by the use of presently available semiconductor vertical processing furnaces results when processing gases are exposed to non-inert furnace components within the process chamber. Typically, wafers must be processed in a controlled environment in order to prevent undesirable oxidation. Ideally, the environment should be nearly inert. For example, inert gas is used during certain annealing processes. However, materials which are not completely inert and that are in fluid contact with the processing gases can produce off-gassing of one or more constituents. Such off-gassing can introduce contaminants into the processing chamber which mix with processing gases. The high temperature conditions and mixing of processing gases within the processing chamber can lead to introduction of such contaminants into the wafers of other semiconductor articles being processed.
There is also a significant problem with regard to the handling of semiconductor processing waste streams. In the case of semiconductor furnaces, the processing chambers are typically supplied with various gases during thermal processing. Since processing pressures are typically atmospheric or sub-atmospheric, the flow of processing gases into the processing chamber requires an approximate flow of spent gases from the processing chamber. These spent processing gases are typically at relatively high temperatures which cause problems in handling and disposal. Thus there is a need for thermal processors having improved waste stream outflows which can be more easily handled.
These and other considerations have led to the improved designs and processes described herein.